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SWI 0x03 — Stop / Sleep

  • Entry: 0x000001A8 (ARM)
  • Status: verified (hardware-checked 2026-07-08: fixture-driven runs on real GBA via the worker's no-blacklist opcode; see Hardware verification section)

Summary

Puts the system into the deeper low-power Stop (a.k.a. Sleep) mode by writing 0x80 to HALTCNT (0x04000301). In Stop mode the CPU, system clock, and video are halted; the machine only wakes on specific external interrupt sources (typically the keypad or a serial/gamepak interrupt). Shares its tail with Halt (SWI 02h) and CustomHalt (SWI 27h).

Parameters

None.

Returns

Returns after HALTCNT is written; resumes on a qualifying wake interrupt.

Clobbered registers

r2 and ip (r12) are used as scratch.

Algorithm

  1. Set r2 = 0x80 (the Stop/Sleep selector value).
  2. Fall through into the shared tail at 0x000001AC: store the byte r2 to HALTCNT at 0x04000301.
  3. Return.

Real constants observed: HALTCNT byte address 0x04000301; Stop value 0x80.

Edge cases & known bugs

  • Callers are expected to disable video/sound/DMA and enable only a valid wake source before invoking Stop; otherwise the system may not wake. Only certain interrupt sources (keypad, gamepak, serial) can resume from Stop.
  • The BIOS itself does not pre-configure the wake source; that is the caller's responsibility.

Hardware verification (2026-07-08)

Fixture-driven runs via the worker's no-blacklist opcode (swf), with wake sources / handlers installed through CpuSet pokes. Raw data: results/blacklist_fixtures1.csv.

Keypad-IRQ fixture (KEYCNT = 0x43FF any-key OR, IE = keypad only, IME = 0): Stop was entered with the link idle and the GBA woke only when a button was pressed (tens of seconds later; repeated SIO clocking during Stop did not wake it with SIO absent from IE). Crucially, the TM0/TM1 cycle counter bracketing the SWI recorded just 57,314 cycles (~3.4 ms) across the whole multi-second stop — the system timers are frozen while stopped (the counted time is entry/exit + post-wake overhead only). IF.keypad is left set after wake, as with Halt.

Cycle count

Wall-clock duration is externally determined and is NOT visible to the timers (frozen during Stop); 57,314 raw cycles were counted across a multi-second stop.

Open questions (need hardware verification)

  • Confirm which interrupt sources actually wake this BIOS revision from Stop and whether any additional register writes are needed before/after.

GBATEK cross-reference

Matches GBATEK SWI 03h Stop/Sleep (HALTCNT 4000301h := 80h). Confirms shared code with Halt/CustomHalt.