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SWI 0x29 — SoundDriverVSyncOn

  • Entry: 0x000018C8 (THUMB; SWI table stores 0x000018C9)
  • Status: verified (hardware-checked 2026-07-08: cycle counts and return registers measured on real GBA; struct layouts remain from static analysis)

Summary

Re-enables the sound-FIFO DMA that SoundDriverVSyncOff stopped. Restarts DMA1 and DMA2 in Sound-FIFO mode so the mixer's PCM buffers stream to FIFO A / FIFO B again. After calling this, the game must resume calling SoundDriverVSync every V-blank. This routine is also invoked internally by SoundDriverInit and by the frequency setup helper.

Parameters / Returns

No explicit arguments. No return value.

Clobbered registers

r0, r1.

Hardware audit (2026-07-08, canary r4–r12 + CPSR snapshot): caller-visible clobbers: r0 = 0x040000C0 (DMA1 destination register address), r1 = 0xB600, r3 preserved. r2, r4–r12, r13, and CPSR (flags and mode) came back bit-identical on every tested path. r11/r12 are explained by the SWI dispatcher (it pushes {r11, r12, lr} — see 10_irq_boot_and_iwram.md) and CPSR by the SPSR restore on return; r2 and r4–r10 must be preserved or restored by the routine itself — where a static note above claims r2 is destroyed, the hardware disagrees at the caller level. Raw data: results/clobber_audit_pass2.csv.

Algorithm

  1. Write 0xB600 to DMA1CNT_H (0x040000C6) and DMA2CNT_H (0x040000D2). 0xB600 = DMA enable (bit15) + repeat (bit9) + 32-bit units (bit10) + start-timing special/Sound-FIFO (bits12–13 = 11), destination fixed. Both channels resume feeding FIFO A and FIFO B from their DMA*SAD mix-buffer bases.
  2. Return.

Note: unlike most sound SWIs, this routine does not verify the SoundArea identity word — it only touches the DMA control registers.

Edge cases & known bugs

  • Assumes DMA1SAD/DMA2SAD and the mixer state are already valid (set by SoundDriverInit). Enabling DMA before the mixer is ready would stream stale data.

Cycle count

Hardware-measured net CPU cycles (worker-ROM harness, TM0/TM1 cascade at F/1, 13-cycle baseline subtracted; identical across 3 runs — see 02_hardware_verification_checklist.md § Measurement setup).

59 cycles.

Open questions (need hardware verification)

  • Whether callers are expected to have re-primed pcmDmaCounter before this call, or whether the next SoundDriverVSync handles resynchronisation.

GBATEK cross-reference

Details GBATEK's SoundDriverVSyncOn: the 0xB600 FIFO-DMA restart written to both DMA1 and DMA2 control high halfwords.